Ferroelectric memories have been developed as one kind of non-volatile semiconductor memory devices having high reliability and low consumption current. Among the ferroelectric memories, one ferroelectric memory having a memory block cell has been noticed from a view point as high integration, and the ferroelectric memory is disclosed in Japanese Patent Publication (Kokai) No. H10-255483, Japanese Patent Publication (Kokai) No. H11-177036 and Japanese Patent Publication (Kokai) No. 2001-257320, for example. In the ferroelectric memory, a memory block cell includes a plurality of memory cells serially connected each other, both ends of a ferroelectric capacitor being connected between a source and a drain in a transistor in each of the memory cells.
On the other hand, micro loading effect in miniaturization processes produces a problem accompanying recent progress of fabricating method for a semiconductor device. The micro loading effect is caused at an area having different and non-periodic sizes of element-patterns in the semiconductor device as comparing with another area in the semiconductor. In the area, a mask material such as a resist is etched over to shrink the mask shape. Therefore, when a memory capacitor is etched in conventional semiconductor memory devices, a problem with difficulty to obtain a desirable etching shape is produced in an end of a memory cell block as comparing with the inner portion of the memory cell block where the memory cells are configured at an equal interval.
To overcome the problem mentioned above, a method to configure a dummy ferroelectric capacitor in a block selector portion disposed between memory cell blocks is proposed in Japanese Patent Publication (Kokai) No. 2002-94022, for example.
However, the block selector portion includes a bit line contact with a high aspect ratio, the bit line contact connecting between a block-selection transistor disposed at one end of the memory block and a bit line formed at an upper portion of the memory capacitor. Accordingly, the dummy capacitor for improving the micro loading effect is disposed in avoiding the bit line contact intentionally. As the bit line contact is configured in the block selector portion in the conventional semiconductor memory device, a problem with a limitation is produced. In the problem, the dummy capacitor cannot necessarily be configured effectively for the micro loading effect. Further, priority for improvement of the micro loading effect causes a problem which the area of the block selector portion is increased beyond necessity.
Moreover, the high aspect ratio of the bit line contact causes a difficult problem for connecting in the contact. Further, hydrogen diffusion to a transistor or the like in a process including hydrogen such as forming a tungsten plug or the like is also a problem.